Last time, we introduced the basic concept of SDC. In the next few issues, we will go over some of the most commonly used SDC commands. Although there are hundreds of SDC commands available, only a dozen or so are typically used in practice. Today, we'll focus on clock-related commands, which play a crucial role in timing analysis and design.
There are several main commands related to clock definitions:
- Create_clock
- Create_generated_clock
- Set_clock_uncertainty
- Set_clock_groups
Before any timing constraints can be applied, clocks must first be defined. In a synchronous circuit, the delay between two sequential elements (like flip-flops) must be less than one clock period. Once the clock is defined, all timing constraints for paths between these elements are automatically set. The definition of a clock generally includes three key elements: waveform, uncertainty, and clock group. These are often referred to as the "three pillars" of clock specification. It's essential to ensure that all three are properly defined when creating a clock.
Create_clock
This command is used to define the source, period, duty cycle, and edge times of a clock signal. For example:
create_clock -name SYSCLK -period 20 -waveform {0 5} [get_ports SCLK]
The waveform specifies the rising and falling edges of the clock. If the period is not specified, the default waveform is {0, period/2}. This helps in accurately modeling the behavior of the clock signal in the design.
Create_generated_clock
Generated clocks are derived from a master clock. They are commonly used for divided or derived clocks, such as those coming from a PLL or divider. For instance:
create_clock -name CLKP -period 10 -waveform {0 5} [get_pins UPLL0/CLKOUT]
create_generated_clock -name CLKPDIV2 -source UPLL0/CLKOUT -master_clock CLKP -divide_by 2 [get_pins UFF0/Q]
These commands allow you to model clocks that are generated from other clocks without creating new clock domains. This is particularly useful for maintaining accurate timing relationships during clock tree synthesis (CTS).
Virtual Clock
A virtual clock is not tied to any physical pin or port but is used to represent an external clock. It is often used for input/output timing constraints, where the actual clock is off-chip. For example:
create_clock -name VCLK -period 10 -waveform {0 5}
Virtual clocks are useful when defining input and output delays, as they provide a more realistic model of how external clocks behave.
Set_clock_uncertainty
This command defines the uncertainty in the arrival time of a clock signal at a sequential element. It helps account for jitter and variations in clock timing. During setup checks, clock uncertainty reduces the effective clock period, while during hold checks, it adds extra margin. For example:
set_clock_uncertainty -from VIRTUAL_SYS_CLK -to SYS_CLK -hold 0.05
set_clock_uncertainty -from SYS_CLK -to CFG_CLK -setup 0.1
Properly setting clock uncertainty ensures that the timing analysis accounts for real-world variations in clock signals.
Set_clock_groups
After defining clocks, it's important to specify their relationships using set_clock_groups. This step is critical for cross-domain timing checks. There are three common options:
- Asynchronous: Two clocks that are not synchronized.
- Physically_exclusive: Two clocks that share the same source.
- Logically_exclusive: Two clocks that are mutually exclusive, such as those controlled by a MUX.
For example:
set_clock_groups -physically_exclusive -group {CLK1 CLK2} -group {CLK3 CLK4}
Correctly defining clock groups ensures accurate timing analysis and avoids errors in static timing analysis (STA).
Clock definition is just the beginning. There are many advanced features and command extensions that require deeper study. Always refer to the official documentation and collaborate with your front-end team to ensure accuracy and consistency in your timing constraints.
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