Eliminating the risks associated with complex network SoC development is no longer a distant dream—it’s now achievable for every design team.
In recent months, I've been writing a series of articles exploring how hardware-accelerated simulation can help verify network system-on-a-chip (SoC) designs before they go to silicon. In this article, we’ll focus on an innovative approach that bridges the gap between front-end and back-end verification in the same network design.
Before diving into the details, let’s take a look at the current market landscape. As new sectors like cloud computing, big data centers, and mobile applications continue to expand, software-defined networking (SDN) has become increasingly popular. Figure 1 shows the growing SDN market, which is expected to grow by 135% over the next two years.
Figure 1. The adoption of SDN is rising due to emerging markets such as cloud computing, big data centers, and mobile applications (Source: Lauro RizzatTI).
SDN has not only increased design complexity but also scaled up the number of ports and the overall size of the design. Figure 2 illustrates the growth in design scale across key market segments.
Figure 2. Design complexity and gate count have risen with new SDN applications (Source: Lauro RizzatTI).
Design teams working on these large-scale SoCs are facing significant challenges. Among the top issues are testing all port configurations, meeting performance and bandwidth expectations, supporting various Ethernet OSI layer protocols, debugging hardware issues, ensuring software reconfiguration works as intended, reducing turnaround time, minimizing verification costs, evaluating power consumption, and shrinking chip packaging.
Traditional software simulation and formal verification tools have limitations when it comes to handling such complex designs. These tools remain essential for IP and subsystem-level validation early in the design cycle, but they fall short when it comes to full-chip verification.
In today's fast-paced and competitive environment, only a hardware-driven verification engine can meet these demands while keeping schedules tight and avoiding revenue loss from delayed chip releases.
As mentioned in my previous articles, hardware-accelerated simulation has emerged as a powerful tool for front-end verification. Modern hardware accelerators offer near-infinite capacity, full visibility into the design, and support for high throughput, fast compilation, and multiple users—all without instrumentation or code changes. They can run in different modes, including internal circuit simulation (ICE), virtual testing, low-power verification, power estimation, and testability design (DFT).
However, when dealing with multi-port SoC designs—such as those with 64 or more ports—the value of ICE has declined significantly. The traditional ICE setup requires external hardware like speed adapters to interface with real-world traffic, which can be slow and unreliable. This leads to higher power consumption, reduced reliability, and limited scalability, often restricting use to a single user. Remote access becomes difficult, and debugging becomes less predictable, making it harder to reproduce and repeat tests.
To address these issues, many teams are shifting to virtual test environments that eliminate hardware dependencies. These environments use software and synthesizable models to simulate real-world conditions, allowing for easy reconfiguration before actual hardware is ready. They support multiple users, remote access, and deployment in data centers, making them ideal for large-scale SoC validation.
Guy Hutchison, a member of the DAC 2016 expert group and assistant vice president at Cavium, noted: “For our design, we rely entirely on virtual technology. Our application doesn’t have a true representative target that can handle 100 Gbps of traffic. So, we use a fully virtual approach for all simulations.â€
Creating a virtual test environment, however, is no small task. To tackle this, companies like Mentor Graphics have developed comprehensive platforms such as VirtuaLAB. This tool supports front-end testing for custom SoC designs and includes features like an Ethernet Packet Generator and Monitor (EPGM), capable of simulating 25GMII, 50GMII, 200GMII, and 400GMII interfaces.
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