Xilinx FPGA development software is ISE. Now its version is updated faster, and everyone's current version is in ISE12.1.
To develop an FPGA using ISE, you need to set some parameters in the development software according to your design content and design target settings. These parameters are essential for successful development.
One of the commonly used options: Keep Hierachy. This parameter has 3 values: NO, YES, Soft.
When using Chipscope for debugging, if the netlist used is inserted into the ICON method, or for debugging purposes, it is best to keep the design hierarchy and select Yes or Soft. The difference between Yes and Soft is:
Keep Hierachy =Yes: Useful for the Debug phase. XST will optimize based on hierarchical synthesis without breaking the hierarchy. All register names are sorted by name. Traslate can find the required constraint objects through the ucf file.
Keep Hierachy = Soft: Keep the hierarchy in synthesis, the tool will break the hierarchy in the MAP phase; but the INSTANCE name is retained.
In the FPGA design prototype verification phase, selecting YES will increase the overall speed of XST.
Common options of the two: register_duplicaTIon + max_fanout + equivalent_register_removal + resource_sharing - allows automatic replication register, set the maximum fan-out, prohibit the sharing of resources. These four options are the most obvious effects on the effects of MAP and PAR. Different designs, their choices are not the same. It depends on the specific design situation. Below is one of the development strategies.
Using duplicate registers when TIming is not met usually improves some bottlenecks. Some optimizations that the synthesizer makes to save area may result in unfavorable timing, so turning off equivalent_register_removal and resource_sharing may improve timing.
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