Detailed analysis of signal integrity and power integrity

I recently came across a question on a forum about power integrity. Many people emphasize signal integrity, but it seems that power integrity isn't given the same attention. This is mainly because for low-frequency applications, switching power supplies are often designed using experience or functional-level simulations, and power integrity analysis doesn’t seem to contribute much. For frequencies between 50MHz and 100MHz, the capacitor design in the switching power supply can usually be handled by rule-of-thumb guidelines, and even some Excel tools provided by chip manufacturers can address the issues in this frequency range. For applications above 100MHz, it’s mostly an IC-level concern, so board-level power integrity simulation doesn’t make much sense unless you have a full chip-to-chip solution with package and chip models. Is that really true? Actually, there's still a lot that can be done with power integrity. Let's take a closer look. Signal Integrity (SI) and Power Integrity (PI) are two related but distinct analyses involved in ensuring the proper operation of digital circuits. In signal integrity, the goal is to ensure that a transmitted '1' looks like a '1' at the receiver (and similarly for '0'). In power integrity, the focus is on making sure that the driver and receiver receive enough current to transmit and receive these signals. Therefore, power integrity can be seen as an integral part of signal integrity. In fact, both are essentially analyses of the correct analog behavior of digital circuits. The necessity of these analyses arises from the limitations of computational resources. If we had infinite computing power, we could analyze the entire circuit once and identify all potential issues. However, in reality, different domain-specific analyses allow us to tackle specific problems without having to consider everything that might go wrong. For example, in signal integrity, the focus is on the path from the transmitter to the receiver. Models can be created for just the transmitter, receiver, and the interconnects in between, which simplifies the simulation process. On the other hand, power integrity simulations can be more complex due to less defined boundaries and their dependence on signal integrity aspects. In signal integrity, the primary concerns are signal quality, crosstalk, and timing. These require detailed models of drivers, receivers, chip packages, and board interconnects (such as traces, vias, and connectors). Driver and receiver models typically include buffer impedance, toggle rate, and voltage swing, and are often represented using IBIS or SPICE models. These models are used alongside interconnect models to simulate signal conditions at the receiver. Interconnects, especially board traces, behave like transmission lines with characteristics such as impedance, delay, and loss. These properties determine how the driver and receiver interact. Electromagnetic properties of the interconnect must be modeled using field solvers or S-parameter models for accurate simulation. Most traces can be modeled as uniform cross-sections, which is sufficient for calculating their impedance. The impedance affects the waveform shape at the receiver, and the most basic signal integrity analysis involves setting up the board stack and determining the correct trace width to achieve the desired impedance. Modeling vias is more complex than modeling traces. Proper via modeling becomes critical when dealing with high-speed signals. Gigabit signals often require three-dimensional field solvers to accurately describe via characteristics. Fast, single-ended signals passing through vias interact strongly with the power distribution network (PDN), which includes stitching holes, capacitors, and plane pairs. Understanding these interactions is essential for accurate signal integrity analysis. Power integrity analysis is more complex than signal integrity because high-frequency energy spreads across the power plane rather than along a single transmission line. At DC, modeling is relatively straightforward, involving trace resistance and planar shapes. However, for high frequencies, analyzing the impedance between power and ground at different points on the PDN requires complex calculations. Factors such as capacitor placement, mounting style, and capacitance value affect the impedance. High-frequency effects, like mounting inductors and planar diffused inductors, must be included for accurate decoupling analysis. A simple lumped decoupling analysis can provide a quick preliminary check, while a distributed analysis ensures that all impedance requirements are met across the board. Signal integrity simulations focus on three main areas: signal quality, crosstalk, and timing. Ensuring clean edges without excessive overshoot or undershoot is crucial, often achieved by adding termination to match the driver and transmission line impedance. For multipoint buses, careful consideration of termination and length variations helps control reflections that could impact signal quality and timing. Crosstalk simulations involve multiple coupled transmission lines and help determine minimum spacing requirements between traces, especially in dense board designs. These simulations are essential for minimizing errors caused by crosstalk. Power integrity simulations include DC voltage drop analysis, decoupling analysis, and noise analysis. DC voltage drop analysis helps identify voltage losses due to copper resistance and high current density regions. Thermal co-simulation can also be used to assess thermal effects. The solution to DC voltage drop issues is usually adding more metal, such as wider traces, additional planes, or more vias. Decoupling analysis aims to minimize the impedance between power and ground at various IC locations on the board. It drives changes in capacitor values, types, and placements to meet low-impedance requirements. Noise analysis investigates how noise propagates through the board and is coupled between vias, including synchronous switching noise caused by signal transitions. The PDN serves not only as a current supply but also as a return path for signals. Vias play a key role in this interaction, as they provide a return path for single-ended signals. The PDN determines the impedance and delay characteristics of vias, which is critical for accurate modeling of high-speed signals like DDR3 and DDR4. Combined SI/PI via models help analyze coupling between vias and signal interactions with the PDN. The PDN is crucial for minimizing noise caused by simultaneous switching of multiple signals (SSN). If the PDN impedance at the IC power pin is too high, switching currents can generate voltage fluctuations that affect the signal itself. Designing a low-impedance PDN through decoupling analysis is essential. Simulating these effects requires both signal integrity and power integrity analyses, often using SPICE or updated IBIS models that account for PDN effects. Analyzing signal integrity and power integrity is vital for successful high-speed digital design. These analyses provide insights into necessary design changes and help achieve optimal performance. As modeling techniques and computing power improve, simulating both types of integrity simultaneously will offer clearer understanding of real-world circuit behavior and design efficiency. Several considerations for power integrity design include: 1. **Power System Noise Margin Analysis**: Most chips specify a normal operating voltage range, typically ±5%. Older regulators may have ±2.5% accuracy, requiring power supply noise to stay within this margin. Calculating the noise margin involves comparing the regulator output voltage with the chip's acceptable range. 2. **Sources of Power Supply Noise**: Power supply noise comes from ripple in the regulated output, delayed response to load current changes, and voltage drops due to parasitic inductance and transient currents. 3. **Capacitor Decoupling Explanations**: Capacitor decoupling is the primary method to reduce power supply noise. From an energy storage perspective, capacitors act as local power sources, releasing stored energy when needed. From an impedance perspective, capacitors reduce AC impedance, helping maintain stable voltages. 4. **Characteristics of Real Capacitors**: Real capacitors have parasitic parameters like ESR and ESL, which become significant at high frequencies. Understanding these characteristics is essential for effective decoupling design. 5. **Local Decoupling Design**: Placing capacitors close to the device across power and ground pins reduces parasitic inductance and ensures stable power delivery during transient current demands. Multiple capacitors in parallel help lower overall impedance. By considering these factors, engineers can design robust power integrity solutions that support reliable high-speed digital systems.

QM9400H-UA

All-in-one motherboard,Industrial computer motherboard,Highly integrated motherboard

HuiZhou GreenTouch Technology Co.,Ltd , https://www.bbstouch.com